验证230GHzSiGe收发机系统工艺信息数据集
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230GHz 太赫兹通信芯片的性能高度依赖工艺参数与物理实现。SiGe 工艺凭借高电子迁移率和成熟集成能力，成为高频段芯片的核心技术路径。本数据集通过工艺规则 + 版图 + 芯片显微照片的组合，首次公开了 230GHz SiGe 收发机的工艺级设计细节，为学术界和工业界提供了可复用的工艺参考，解决了 “设计 - 工艺 - 流片” 协同优化的关键问题，加速太赫兹芯片从设计到制造的落地。该数据集聚焦230GHz SiGe 收发机芯片工艺实现，由清华大学东主楼微电子学研究所团队于 2021 年 4 月至 2023 年 4 月采集生成，包含 3 个文件，总数据量约4.57MB，覆盖工艺文档、版图及芯片实物信息。数据产生方法，工艺文档获取：直接引用晶圆代工厂提供的SiGe 工艺描述文件（10-3.pdf），涵盖金属层定义、器件电学特性等设计规则；版图设计：使用 Cadence Virtuoso 完成芯片版图绘制（10-1.png），严格遵循 SiGe 工艺规则，包含射频模块、数字电路及焊盘布局；芯片显微拍摄：通过光学显微镜采集流片后芯片的显微照片（10-2.png），直观展示物理结构与模块分区。数据主要内容包括工艺设计文档（10-3.pdf）：代工厂提供的 PDK 工艺库文件，定义器件参数与制造规则；芯片版图截图（10-1.png）：Virtuoso 版图界面截图，反映芯片物理设计全貌（如面积、层叠结构）；芯片显微照片（10-2.png）：实际流片芯片的光学显微图像，验证设计的物理实现与模块布局。数据集完全共享，适用于芯片设计团队参考工艺规则优化版图，或高校作为教学案例讲解 “设计 - 工艺” 映射关系。其核心意义在于将抽象工艺规则与具体芯片实物结合，为 230GHz SiGe 芯片的工艺选型、版图优化及流片验证提供直接数据支撑，推动太赫兹通信技术的工程化发展。
The performance of 230GHz terahertz communication chips is highly dependent on process parameters and physical implementation. The SiGe (silicon-germanium) process, with its high electron mobility and mature integration capabilities, has become the core technical pathway for high-frequency band chips. This dataset combines process rules, layout designs and chip photomicrographs, and for the first time publicly discloses the process-level design details of a 230GHz SiGe transceiver, providing reusable process references for both academic and industrial communities, solving the key issue of collaborative optimization across "design-process-fabrication", and accelerating the translation of terahertz chips from design to manufacturing. This dataset focuses on the process implementation of 230GHz SiGe transceiver chips, and was collected and generated by the team from the Institute of Microelectronics, East Main Building, Tsinghua University, between April 2021 and April 2023. It consists of 3 files with a total data volume of approximately 4.57 MB, covering process documents, layouts and physical chip information. Data generation methods: 1. Acquisition of process documents: Directly citing the SiGe process description document (10-3.pdf) provided by the wafer foundry, which covers design rules such as metal layer definitions and device electrical characteristics; 2. Layout design: Completing chip layout drawing (10-1.png) using Cadence Virtuoso, strictly adhering to SiGe process rules, including RF modules, digital circuits and pad layouts; 3. Chip microphotography: Collecting photomicrographs of fabricated chips (10-2.png) using an optical microscope, which intuitively displays the physical structure and module partitioning. The main contents of the dataset include: - Process design documents (10-3.pdf): PDK (Process Design Kit) process library files provided by the foundry, defining device parameters and manufacturing rules; - Chip layout screenshots (10-1.png): Screenshots of the Virtuoso layout interface, reflecting the overall physical design of the chip (such as area and stack structure); - Chip photomicrographs (10-2.png): Optical microscopic images of actually fabricated chips, verifying the physical implementation and module layout of the design. This dataset is fully shared, suitable for chip design teams to reference process rules to optimize layouts, or for universities to use as teaching cases to explain the "design-process" mapping relationship. Its core significance lies in combining abstract process rules with specific physical chip samples, providing direct data support for process selection, layout optimization and fabrication verification of 230GHz SiGe chips, and promoting the engineering development of terahertz communication technology.
