验证150GHzCMOS收发机工艺信息数据集
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在 150GHz 太赫兹通信芯片研发中，工艺参数直接决定芯片的性能、功耗与制造成本。CMOS 工艺因低成本、高集成度优势成为高频收发机的主流选择，但 28nm 及以下节点的工艺设计规则（DRC）、版图实现与流片后的物理验证是技术难点。本数据集通过工艺文档 + 版图 + 芯片实物照片的组合，首次公开了 150GHz CMOS 收发机从设计到制造的全流程工艺信息，为学术界和工业界提供了可复用的工艺参考框架，助力解决高频芯片 “设计 - 工艺 - 流片” 协同优化的关键问题，该数据集是 “验证 150GHz CMOS 收发机工艺信息” 的核心佐证材料，主要面向高频通信芯片工艺实现、集成电路制造与物理设计领域的研究需求建设。数据依托清华大学科研团队，于2023 年 4 月 2 日通过台积电（TSMC）28nm CMOS 工艺及 Cadence 版图设计工具产生，包含 4 个文件，总数据量约2.36MB，无衍生子文件夹。数据采集与生成流程紧密围绕芯片工艺实现链：版图设计：使用Cadence Virtuoso 软件完成芯片版图绘制（5-2 芯片版图照片.png），严格遵循 TSMC 工艺规则，涵盖射频前端、基带电路、电源网络等模块的物理布局；流片与拍照：将版图文件提交台积电进行流片制造，通过光学显微镜拍摄实际芯片照片（5-3 芯片照片.pdf）及端口标识照片（5-4 芯片照片 - 端口.pdf），直观呈现芯片实体结构与功能分区。数据主要内容：数据集包含四类关键资源：工艺设计文档：文件 5-1：TSMC 28nm 工艺的 DRC 规则手册，详细规定了晶体管间距、金属线宽、过孔数量等物理设计参数，是版图合规性的基础依据。 芯片版图数据：文件 5-2：以.png 格式呈现的版图截图，展示芯片的完整物理设计，包括射频模块（如功率放大器、混频器）、基带模块及焊盘布局，可用于分析布局对信号完整性的影响。 芯片实物照片：文件 5-3：宏观芯片照片，清晰显示流片后的芯片实体及封装框架，证明设计已成功转化为物理器件；文件件 5-4：端口特写照片，标注了电源（VDD）、接地（GND）、射频输入 / 输出（RF IN/OUT）等关键引脚位置，为芯片测试与系统集成提供指引。数据体量与格式总数据量：约 2.36MB，其中 PDF 文档（工艺规则与照片）占主要存储体积，版图截图为轻量化图片格式； 文件格式：PDF：用于工艺文档和照片展示，支持跨平台查看；PNG：用于版图截图，方便图像编辑与尺寸测量。工艺文档获取：
In the development of 150 GHz terahertz communication chips, process parameters directly determine chip performance, power consumption and manufacturing cost. CMOS process has become the mainstream choice for high-frequency transceivers due to its low cost and high integration, but process Design Rule Check (DRC) rules, layout implementation and post-fabrication physical verification for 28 nm and smaller nodes remain technical challenges. This dataset, combining process documents, layouts and actual chip photographs, publicly discloses the full-process manufacturing information of 150 GHz CMOS transceivers from design to fabrication for the first time. It provides a reusable process reference framework for both academic and industrial communities, helping to address the key issue of collaborative optimization in the "design-process-fabrication" workflow for high-frequency chips. As the core supporting material for verifying the process information of 150 GHz CMOS transceivers, this dataset is developed to meet the research needs in the fields of high-frequency communication chip process implementation, integrated circuit manufacturing and physical design. Supported by the research team from Tsinghua University, this dataset was generated on April 2, 2023 using TSMC 28 nm CMOS process and Cadence layout design tools. It contains 4 files with a total data volume of approximately 2.36 MB and no nested subfolders. The data collection and generation process closely follows the chip process implementation chain: Layout Design: The chip layout was drawn using Cadence Virtuoso software (5-2 Chip Layout Photo.png), strictly complying with TSMC process rules, covering the physical layout of modules such as RF front-end, baseband circuit and power supply network; Fabrication and Photography: The layout files were submitted to TSMC for fabrication, and actual chip photographs (5-3 Chip Photo.pdf) and port identification photographs (5-4 Chip Photo - Port.pdf) were taken using an optical microscope, which intuitively present the physical structure and functional partitions of the chip. Main Data Content: The dataset includes four types of key resources: Process Design Documents: File 5-1: TSMC 28 nm process DRC rule manual, which specifies physical design parameters such as transistor spacing, metal line width and via count in detail, serving as the basic basis for layout compliance. Chip Layout Data: File 5-2: Layout screenshots in PNG format, showing the complete physical design of the chip, including RF modules (such as power amplifiers, mixers), baseband modules and pad layout, which can be used to analyze the impact of layout on signal integrity. Actual Chip Photographs: File 5-3: Macro chip photographs, clearly showing the post-fabrication chip entity and packaging framework, proving that the design has been successfully transformed into physical devices; File 5-4: Close-up photographs of ports, marking the positions of key pins such as power supply (VDD), ground (GND), RF input/output (RF IN/OUT), providing guidance for chip testing and system integration. Data Volume and Format Total Data Volume: Approximately 2.36 MB, among which PDF documents (process rules and photographs) occupy the main storage space, while layout screenshots are lightweight image formats; File Formats: PDF: Used for process documents and photo display, supporting cross-platform viewing; PNG: Used for layout screenshots, facilitating image editing and dimension measurement. Acquisition of Process Documents:
