Spiking Neural Network Hypergraphs with Spike Frequency Data

Content

These hypergraphs constitute a set of benchmarks for mapping Spiking Neural Networks (SNNs) on neuromorphic hardware (e.g. [1, 2]).

Refer to [3] for how they were generated.

Included hypergraphs:

Name / Metric
16k-model
64k-model
256k-model
1M-model
16M-model
lenet
alexnet
vgg11
mobilenet v1
allen v1
16k-rand
64k-rand
256k-rand

nodes count
20k
110k
216k
302k
991k
14k
208k
194k
6.9M
231k
16k
64k
256k

pins count
766k
23M
90M
256M
1.9B
875k
145M
133M
577M
70M
2.1M
12.6M
67.4M

average hyperedge cardinality
37.3
210.3
417.2
848.1
1.9k
63.2
696.2
688.3
83.5
304.7
128
192
256

Format

Hypergraphs are stored in a custom binary SNN hypergraph format (.snn).A compact binary format for directed hypergraphs with exactly one source node per hyperedge.

File layout (little-endian):

first 32bits: uint32 node_count total number of nodes

second 32bits: uint32 edge_count number of hyperedges

repeated edge_count times:

32bits: uint32 dst_count number of destination nodes

32bits: uint32 src source node id (0-based)

32*dst_count bits: uint32 dst[dst_count] destination node ids (0-based)

32bits: float weight hyperedge weight

Notes:

node ids are 0-based

hyperedges are directed: src → dst(s)

the format supports exactly one source per hyperedge

no vertex weights or metadata are stored

References

[1] - F. Akopyan et al., "TrueNorth: Design and Tool Flow of a 65 mW 1 Million Neuron Programmable Neurosynaptic Chip," in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 34, no. 10, pp. 1537-1557, Oct. 2015, doi: 10.1109/TCAD.2015.2474396.[2] - M. Davies et al., "Loihi: A Neuromorphic Manycore Processor with On-Chip Learning," in IEEE Micro, vol. 38, no. 1, pp. 82-99, January/February 2018, doi: 10.1109/MM.2018.112130359.[3] - M. Ronzani and C. Silvano, "A Case for Hypergraphs to Model and Map SNNs on Neuromorphic Hardware." 2026. Available: https://arxiv.org/abs/2601.16118