Data for <b>Simulating and Optimizing Tapped Delay Lines </b><b>for Time-to-digital Converters in FPGA using a </b><b>Precision Model based on Circuit Characteristics</b>

This is the data used to produce results for <b>Simulating and Optimizing Tapped Delay Lines </b><b>for Time-to-digital Converters in FPGA using a </b><b>Precision Model based on Circuit Characteristics</b>. It contains TDL delay and skew obtained from Vivado.

本数据集为支撑《基于电路特性精确模型的FPGA（Field-Programmable Gate Array）内时间数字转换器（Time-to-digital Converters, TDC）抽头延迟线（Tapped Delay Lines, TDL）仿真与优化》研究结果的配套数据，包含从Vivado工具中获取的TDL延迟与时偏参数。