验证150GHzCMOS收发机测试板设计数据集
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在 150GHz 芯片研发中，测试板是连接芯片与测试仪器的关键桥梁，其设计质量直接影响实测数据的准确性。高频下（尤其是太赫兹频段），PCB 板材损耗、引脚寄生参数及打线（bonding）工艺可能引入信号失真，导致测试结果偏离真实芯片性能。本数据集提供了完整的测试板设计工程文件与物理连接证据，解决了 “芯片测试平台搭建难、信号完整性验证不足” 的行业痛点，为高频芯片的功能评估与性能测试提供了标准化参考方案，加速研发流程中的 “设计 - 测试” 迭代。该数据集聚焦150GHz CMOS 收发机芯片测试载体设计，主要面向高频芯片测试平台开发、PCB 设计与信号完整性优化领域的研究需求建设。数据由清华大学团队基于Altium Designer PCB 设计软件及芯片物理连接工艺产生，包含 6 个文件，总数据量约19.2MB。数据生成流程结合EDA 设计与物理实现：原理图设计：使用 Altium Designer 绘制测试板原理图（3-5.SchDoc），定义芯片引脚与测试端口（如射频接口、电源引脚）的电气连接，同步创建原理图库文件（3-6.SchLib）管理器件符号；PCB 布局与布线：基于原理图生成 PCB 设计文件（3-2.PcbDoc），采用高频板材（如 Rogers 4350B）降低介质损耗，优化射频路径布线以减少寄生电感 / 电容，并通过工程文件（3-4.PrjPcb）管理设计版本；物理验证：通过 “3-1 bonding” 文件夹内的图片，记录芯片与测试板之间的金线键合（bonding）过程及成品照片，确保电气连接的可靠性。 数据主要内容，数据集包含两类核心资源：测试板设计文件（Altium Designer 工程文件）：原理图文件（.SchDoc）：展示测试板的电路架构，包括电源管理模块、射频信号链路及测试点布局；PCB 设计文件（.PcbDoc）：包含多层板叠层结构、射频走线阻抗控制参数（如 50Ω 微带线）及焊盘布局；库文件（.SchLib/.PcbLib）：存储芯片封装、接插件等器件的电气模型与物理参数，确保设计复用性。物理连接证据：“3-1 bonding” 文件夹：包含芯片与测试板键合后的显微照片，直观呈现金线连接形态（如线长、弧度），用于验证机械可靠性与信号传输路径的物理实现。数据体量与应用：数据量：约 19.2MB，主要为 Altium Designer 工程文件（含二进制数据），体积较大但完整保留设计细节；工具依赖：需通过 Altium Designer 打开设计文件，支持查看、修改布线或生成制造文件（如 Gerber）；应用场景：企业研发：直接复用测试板架构，或基于布局经验优化自有芯片的测试平台，降低开发成本；测试服务机构：参考 bonding 工艺与端口设计，提升 150GHz 芯片的自动化测试效率。本数据集完全开放共享，首次公开了 150GHz 频段测试板的全流程设计数据，填补了高频测试平台设计数据的空白。
In the development of 150GHz chips, the test board serves as a critical bridge connecting the chip and test equipment, and its design quality directly affects the accuracy of measured data. At high frequencies (especially in the terahertz frequency band), PCB substrate loss, pin parasitic parameters, and bonding process may introduce signal distortion, causing test results to deviate from the actual performance of the chip. This dataset provides complete test board design engineering files and physical connection evidence, addressing the industry pain points of "difficulty in building chip test platforms and insufficient signal integrity verification". It offers standardized reference solutions for functional evaluation and performance testing of high-frequency chips, accelerating the design-test iteration in the R&D process. This dataset focuses on the design of test carriers for 150GHz CMOS transceiver chips, and is constructed to meet the research needs in the fields of high-frequency chip test platform development, PCB design, and signal integrity optimization. The data was generated by the Tsinghua University team based on Altium Designer PCB design software and chip physical connection processes, containing 6 files with a total data volume of approximately 19.2 MB. The data generation process combines EDA design and physical implementation: 1. Schematic Design: Use Altium Designer to draw the test board schematic (3-5.SchDoc), define the electrical connections between chip pins and test ports (such as RF interfaces and power pins), and simultaneously create a schematic library file (3-6.SchLib) to manage component symbols; 2. PCB Layout and Routing: Generate the PCB design file (3-2.PcbDoc) based on the schematic, adopt high-frequency substrates (such as Rogers 4350B) to reduce dielectric loss, optimize RF path routing to reduce parasitic inductance/capacitance, and manage design versions through the engineering file (3-4.PrjPcb); 3. Physical Verification: Record the gold wire bonding process between the chip and the test board and finished product photos through the images in the "3-1 bonding" folder, ensuring the reliability of electrical connections. Main Content of the Dataset The dataset includes two core types of resources: 1. Test Board Design Files (Altium Designer Engineering Files): - Schematic Files (.SchDoc): Show the circuit architecture of the test board, including power management modules, RF signal links, and test point layouts; - PCB Design Files (.PcbDoc): Contain multi-layer board stack-up structures, RF trace impedance control parameters (such as 50Ω microstrip lines), and pad layouts; - Library Files (.SchLib/.PcbLib): Store electrical models and physical parameters of components such as chip packages and connectors, ensuring design reusability. 2. Physical Connection Evidence: - "3-1 bonding" Folder: Contains micrographs of the chip bonded to the test board, intuitively presenting the morphology of gold wire connections (such as wire length and arc), which are used to verify mechanical reliability and the physical implementation of signal transmission paths. Data Volume and Applications - Data Volume: Approximately 19.2 MB, mainly consisting of Altium Designer engineering files (including binary data), which have a large volume but fully retain design details; - Tool Dependencies: Design files can only be opened with Altium Designer, which supports viewing, modifying routing, or generating manufacturing files (such as Gerber); - Application Scenarios: - Enterprise R&D: Directly reuse the test board architecture, or optimize the test platform for their own chips based on layout experience to reduce development costs; - Test Service Institutions: Refer to bonding processes and port designs to improve the automated test efficiency of 150GHz chips. This dataset is fully open and shared, and for the first time discloses the full-process design data of 150GHz frequency band test boards, filling the gap in design data for high-frequency test platforms.
