基于存算一体的可扩展异构多核SoC芯片数据集

在存算一体芯片的核心外围辅助电路优化设计及测试上，北京大学负责大规模存算一体异构多核SoC片上集成的总体工作，中科院微系统所和北京大学分别负责大规模相变存储器和阻变存储器存算一体异构核设计、交互通信的工作，北方集成电路创新中心负责器件流片工作。在数据测试上，根据测试芯片和测试开发板，使用测试程序测试容量、算力和性能指标、算法运算效果，使用万用表和测试程序测量运算效率。利用了B1500半导体参数分析仪，16862A逻辑分析仪，N6705C器件电流分析仪，34470A数字万用表，DS0X2024A示波器，数据处理上使用了Matlab、Python、Origin等专业数据软件。数据集中包括SoC架构支持计算核心种类，支持计算核心数量（存算一体阵列）；包含片上网络部件、忆阻器、通信接口等，存算一体单芯片容量，算力，芯片处理能效；SoC芯片仿真平台支持存储介质种类等。总数据量120MB.Regarding the optimized design and testing of core peripheral auxiliary circuits for compute-in-memory (CIM) chips, Peking University is responsible for the overall work of on-chip integration of large-scale compute-in-memory heterogeneous multi-core SoCs. The Institute of Microelectronics of the Chinese Academy of Sciences and Peking University are respectively in charge of the design and interactive communication of compute-in-memory heterogeneous cores based on large-scale phase-change memory (PCM) and resistive random-access memory (RRAM). The Northern Integrated Circuit Innovation Center is responsible for device tape-out work. For data testing, based on the test chips and test development boards, test programs are used to evaluate capacity, computing power, performance indicators and algorithm operation effects, while a multimeter and test programs are applied to measure operation efficiency. The following instruments were utilized: B1500 semiconductor parameter analyzer, 16862A logic analyzer, N6705C device current analyzer, 34470A digital multimeter, and DS0X2024A oscilloscope. Professional data processing software including Matlab, Python and Origin were adopted for data processing. The dataset covers: the types of computing cores supported by the SoC architecture and the number of supported computing cores (compute-in-memory arrays); on-chip network components, memristors, communication interfaces and other related modules; the capacity, computing power and processing energy efficiency of a single compute-in-memory chip; the types of storage media supported by the SoC chip simulation platform, and other relevant information. The total data volume of the dataset is 120 MB.

搜集汇总

背景与挑战

背景概述

该数据集聚焦于基于存算一体的可扩展异构多核SoC芯片，涵盖芯片外围辅助电路优化设计、测试及大规模片上集成，涉及相变存储器和阻变存储器存算一体异构核设计、交互通信等。内容包括SoC架构、计算核心种类与数量、存算一体阵列、片上网络部件、忆阻器、通信接口，以及容量、算力、芯片能效等测试指标，总数据量约120MB。