100G PAM4 PHY收发机原型芯片测试数据集

本课题面向数据中心光电互连的需求，在带宽扩展技术、高速低功耗采样技术、收发机组合均衡技术、低抖动多相时钟产生技术、低功耗时钟恢复技术等方面展开研究；突破带宽受限、能量效率低、均衡能力不足、时钟信号质量差等挑战；设计实现100G PAM4发射机和接收机，完成100G PAM4 PHY原型芯片测试。数据集名称：100G PAM4 PHY收发机原型芯片测试数据集，主要测试了编码类型数据速率、差分输出、摆幅等9项指标的完成情况。This research targets the demands of optoelectronic interconnection in data centers, conducting studies on bandwidth expansion technology, high-speed low-power sampling technology, transceiver joint equalization technology, low-jitter multi-phase clock generation technology, low-power clock recovery technology, and other related technologies. It breaks through challenges such as limited bandwidth, low energy efficiency, insufficient equalization capability, and poor clock signal quality. A 100G PAM4 transmitter and receiver were designed and implemented, and the testing of the 100G PAM4 PHY prototype chip was completed. Dataset Name: 100G PAM4 PHY Transceiver Prototype Chip Test Dataset. This dataset mainly tests the completion status of 9 indicators including coding type, data rate, differential output, output swing, and other relevant parameters.

搜集汇总

背景与挑战

背景概述

该数据集面向数据中心光电互连需求，针对100G PAM4 PHY收发机原型芯片进行了测试。测试内容涵盖了编码类型数据速率、差分输出、摆幅等9项关键指标的完成情况。